Schlagwort-Archive: SEU

Tools to verify radiation hardened designs in VHDL

Publiziert am 30. September 2013 von admin

During my bachelor thesis tools were needed to verify the behaviour of radiation hardened hardware descriptions. For that two tools were programmed: The first tool simulates the behaviour of the description as a behavioural simulation in Modelsim and induces Single … Weiterlesen →

Veröffentlicht unter Allgemein, Python, VHDL | Verschlagwortet mit , , , , , , , , , , | Schreib einen Kommentar