Status: in process
A minimal instruction set computer is a cpu with only a few instructions and opcodes.
The idea is to develop a simple processor written in VHDL and implement it on the Digilent Atlys Board.
The design mythology should be the KISS „keep it simple stupid“ principle.
The design goal is to develop a processor with a good balance in simplicity and performance.
The processor instructions should be:
- load loads constant to register
- add add register x1, register x2
- sub substract register x1, register x2
- shift right shift register x 1 bitto the right
- xor xor operation between register x1, register x2
- or or operation between register x1, register x2
- and and operation between register x1, register x2
- jump jump to address x
- call call subroutine
- return return from subroutine
- branch branch if bit x in sreg is set
- in get data from databus
- out write data to databus
- nop no operation
The green instructions are implemented at this point.
The structure of the processor design should be a datapath design as shown in the figure on top. The main part is the instruction decode block which gets the instructions and controls the dataflow. The opcodes are optimised for the instruction decode unit to get a simple decode logic.
The data path
Everytime an instruction is perfomed it goes through the data path. Each normal instruction is performed in one clock cycle. Branches and jumps will take more than one clock cycle scince the instruction pipeline has to be refilled
When in example an add instruction is performed the instr_dec block decodes the opcode. Then the instr_dec block configures the datapath. First the right register in the reg_file are selected. Then an addition is performed in the alu and within one clock cycle the result is written back to the reg_file into the target register.
For the sources and a detailed description: