I was looking for a way to learn something about analog integrated circuit design, without the need of expansive simulators or technology models.
I work often with LTspice. But the problem is that the default nmos4 and pmos4 models are not good enought for the kind of effects you want to see in our transistor geomentries. So I found that there are some predictive technology models available for free at (http://ptm.asu.edu/) in different structure sizes and technologies. These are Spice models which can be used with LTspice. I want to give here a entry in simulating such integrated design with LTspice for educational purposes.
Setting up LTspice
Including the PTM model in LTspice is easy we just have to use the .include Spice directive to add the PTM model. I am using in this articles the 65nm BSIM4 model card for bulk CMOS. This model can be downloaded here.
This model includes NMOS and PMOS model.
To get them into our schematic we just add the NMOS4 or PMOS4 and rename them to nmos, pmos like the models in the included model file.
A first simulation getting NMOS characteristics
First we want to simulate the basic NMOS characteristics. To do that we sweep the drain source voltage and measure the drain current. We do this for different gate source voltages to get for each gate source voltage a curve. Our NMOS is the NMOS4 which is named nmos and has a width of 2u and a a length of 1u.
To achieve that we do a dc sweep simulation with VDS as voltage source from 0 to 2.4V. We also do a parameter sweep for the parameter VGS for 0.4V, 0.6V, 0.8V, 1.0V and 1.2V. Then we run the simulation and measure the drain current.
Now we can look at the plot and we will different functions which saturate with increasing VDS at a drain current. The section before saturation is called linear region and when it saturates it is called saturation. With increasing VGS we get higher current curves (In our plot is green 0.4V, blue 0.6V, red 0.8V light blue 1.0V and magenta 1.2V).
The reason that the current does not saturate at one current and increases slightly with increasing VDS is called the early effect or channel length modulation.
That is it we got our first simulation working…