For documentation I often need a picture of the blackbox view from a Verilog module. So I wrote a little tcl tool which automates the task. The tool takes a Verilog file and gives a blackbox view out which can be saved.
tclsh drawBlackbox.tcl path/to/file/file.v
The saved ouptut looks like the picture above (there for a counter example).
The Tool can be found under my VerilogModules GitHub page.
The counter.v can also be found in the GitHub page and a detailed documentation will follow there.
Until now the tool only works for verilog 2001 ANSI C Style input and output declaration.
See here at Page 28